1. Field of the Invention
The present invention relates to electronic circuits for analog to digital conversion, and more specifically to electronic circuits for analog to digital or digital to analog conversion using state sensitive components that exhibit a memory characteristic.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
Analog-to-digital signal converters (ADC) are relatively well known in the industry. Such devices sample an analog input signal at a given time (tsample) and convert the sample to a digital value representative of this signal. As the analog input amplitude varies over time, the discrete samples of this input signal result in a string of digital values that allow the continuously varying analog signal to be represented in the digital domain for subsequent processing using automated computing methods. The inverse, digital-to-analog signal converters (DAC) are also relatively well known. As the name implies, a DAC accepts a digital value input and produces an analog amplitude output that is representative of the digital input. If a string of digital values is supplied to the input of a DAC, the output is a reconstructed analog signal waveform. Typically, the greater the numeric value, the greater the analog signal output. The frequency at which the digital values are supplied to the DAC influences the frequency of the resulting analog waveform.
Examples of well-known ADCs include flash, successive-approximation, slope, and ramp type converters. Common to each is the use of comparator banks, clocks, counters, and other passive components that utilize a significant amount of space within (and without) an IC package and can be rather costly. Moreover, the large number of components adversely affects the speed at which such devices may operate. Examples of DACs include binary-weighted, R-2R ladder, and successive-approximation type converters. Like ADCs, DAC components are relatively large and costly as well and, consequently, can consume a significant amount of power.
In addition, such devices (ADCs and DACs) are volatile, meaning that when the power is removed the circuit “forgets” its previous state. Consequently, additional circuitry is required when a sample-and-hold functionality is desired. For example, it may be desirable to use an ADC on the input of an oscilloscope to sample a continuously varying analog input signal over a fixed period of time, and to retain this signal for subsequent analysis. A traditional ADC will require full conversion of the signal to a digital value at discrete time periods over this fixed period of time, and storage of the digital signal values in additional memory registers for use in the signal analysis. The speed at which this full conversion occurs can be limiting to the accuracy with which the ADC functions in this regard. Likewise, when recreating an analog waveform (for example, a waveform generator) using a DAC it is necessary to retain the digital input values in additional memory registers. Unless the memory registers are non-volatile, the digital values will have to be recreated or reinitialized whenever the circuitry is de-energized. Moreover, DAC devices incur substantial latency in the conversion process thereby limiting the effective frequency at which conversion may occur.
The present invention addresses these aforementioned shortcomings in ADC/DAC devices by utilizing state-sensitive cells in a non-volatile memory capacity, which affords circuits having fewer components and a reduced amount of physical space.